1. Field of the Invention
The present invention relates to a solid-state image sensor, particularly relates to a solid-state image sensor provided with a divided photoelectric conversion part.
2. Description of the Related Art
Recently, a solid-state image sensor used for a digital camera, digital VTR and others has attracted a great deal of attention. Heretofore, a solid-state image sensor was roughly classified into a MOS type and a CCD type according to a system of a transport layer for transferring a photoelectrically converted signal charge.
Of these solid-state image sensors, particularly a CCD-type solid-state image sensor has been recently used for electronic equipment such as camera-integrated VTR, a digital camera and a facsimile and technical development for enhancing the characteristics is still currently made.
For one of such solid-state image sensors, there is a solid-state image sensor compatible with a CMOS manufacturing process (hereinafter called a CMOS sensor) (for example, refer to pages 120 to 125 in the July number in 1997 of the Nikkei Microdevice). This CMOS sensor can be operated by a single power source of 5 V or 3.3 V and is provided with characteristics that the power consumption is low, the CMOS sensor can be manufactured in a general CMOS manufacturing process, can be mounted in the identical chip together with a signal processing circuit and other peripheral circuits and is compatible with a CMOS manufacturing process.
FIGS. 10A and 11A are sectional views respectively showing a basic cell (picture element) of a CMOS sensor. FIG. 10B is a potential phase diagram when signal charges are accumulated in a photoelectric conversion part and FIG. 11B is a potential phase diagram when signal charges in the photoelectric conversion part are reset.
As shown in FIG. 10A, the basic cell (picture element) of the CMOS sensor is provided with a P-type semiconductor substrate 301, a P-type well layer 302 which is formed inside the P-type semiconductor substrate 301 and a part of which is exposed on the surface of the P-type semiconductor substrate 301, P+-type semiconductor regions 303 and 323 formed on the P-type well layer 302, exposed on the surface of the P-type semiconductor substrate 301 and functioning as an element separating region, an N+-type semiconductor region 306 surrounded by the P-type well layer 302 and the P+-type semiconductor region 303 and functioning as a photoelectric conversion part, an N+-type semiconductor region 305 surrounded by the P-type well layer 302 and the P+-type semiconductor region 323 and functioning as a drain of MOSFET for control 401, the MOSFET for control 401 having a gate electrode located opposite to the exposed surface of the P-type well layer 302 exposed on the surface of the P-type semiconductor substrate 301, first MOSFET 402 functioning as a source-follower amplifier and second MOSFET 403 functioning as a horizontal selecting switch.
The basic cell of the CMOS sensor is connected to an external circuit via the second MOSFET 403.
The external circuit is composed of third load MOSFET 404 that receives the load of the source-follower amplifier, MOSFET for transferring dark output 405, MOSFET for transferring light output 406, a capacitor for accumulating dark output 407 connected to a source or a drain of the MOSFET for transferring dark output 405 and a capacitor for accumulating light output 408 connected to a source or a drain of the MOSFET for transferring light output 406.
The second MOSFET 403 is connected to the third load MOSFET 404. The MOSFET for transferring dark output 405 and the MOSFET for transferring light output 406 are connected to a node between the second MOSFET 403 and the third load MOSFET 404.
The first MOSFET 402, the second MOSFET 403 and the third load MOSFET 404 are connected in series between line sources VDD and VSS. The N+-type semiconductor region 306 is connected to a gate of the first MOSFET 402.
The P+-type semiconductor regions 303 and 323 are grounded and the N+-type semiconductor region 305 is connected to a line source VDD.
The basic cell 450 shown as a picture element in FIGS. 10 and 11 of the CMOS sensor is arranged in a matrix and a CMOS cell series is formed. Each basic cell 450 is connected to vertical registers (V-registers) 451, horizontal registers (H-registers) 452, the load transistor 404 and an output line 453 as shown in FIG. 12A.
The load transistor 404 shown in FIG. 12A is identical to the load MOSFET 404 shown in FIGS. 10 and 11.
The output line 453 is connected to each MOSFET 405, 406 and each capacitor 407, 408 respectively shown in FIGS. 10 and 11 via vertical selecting switch MOSFET 455 as a vertical selecting switch selected by the horizontal register 452.
FIG. 12B shows connection inside the basic cell (or a picture element) and the same reference number is allocated to a component corresponding to that in FIGS. 10 and 11. As shown in FIG. 12B, a control pulse xcfx86R is input to a gate of the MOSFET for control 401, an address signal X is input to a gate of the second MOSFET 403 and the load transistor 404 and the output line 453 are connected to a source of the second MOSFET 403.
Next, referring to FIGS. 10 and 11, a method of operating the CMOS sensor configured as described above will be described.
First, as shown in FIG. 11, the control pulse xcfx86R applied to the gate of the MOSFET for control 401 in reset time is set to the voltage of a high level and the N+-type semiconductor region 306 is reset to source voltage VDD.
As shown in FIG. 10 after a reset is finished, the control pulse xcfx86R to the MOSFET for control 401 is set to the voltage of a low level.
In the N+-type semiconductor region 306 that functions as a photoelectric conversion part, kTC noise is caused by the reset, however, this can be removed by sampling and accumulating dark output before signal charges are transferred and eliminating difference between the dark output and light output.
In the succeeding accumulation period of signal charges, in the N+-type semiconductor region 306 that functions as a photoelectric conversion part, when an electron-hole pair is caused by incident light, electrons are accumulated in a depletion layer and the hole is discharged via the P-type well layer 302. Grid-like hatching showing electric potential lower than the source voltage VDD shows that this region is not depleted.
The electric potential of the N+-type semiconductor region 306 that functions as a photoelectric conversion part varies according to the number of accumulated electrons. A photoelectric transfer characteristic satisfactory in linearity can be acquired by outputting the variation of the electric potential to the second MOSFET 403 via the source of the first MOSFET 402 by the source-follower operation of the first MOSFET 402.
In the solid-state image sensor compatible with the CMOS manufacturing process, the electric potential of the N+-type semiconductor region 306 that functions as a photoelectric conversion part varies according to the number of accumulated electrons and the variation of the electric potential is output to the second MOSFET 403 via the source of the first MOSFET 402 by the source-follower operation of the first MOSFET 402.
In this case, if the quantity of signal charges is Q, the parasitic capacity of the N+-type semiconductor region 306 that functions as a photoelectric conversion part is C and output voltage is V, V=Q/C. FIG. 13 shows relation among the quantity of incident light, electric potential and output voltage.
However, as shown in FIG. 10, as a photoelectric conversion part is formed by the N+-type semiconductor region 306 in the solid-state image sensor compatible with the CMOS manufacturing process, there is a defect that the parasitic capacity C of the photoelectric conversion part increases as a result even if the area of the photoelectric conversion part is simply increased and the variation V of the electric potential by signal charges cannot be increased by expected quantity.
The invention is made to solve the problem and particularly, the object is to provide a solid-state image sensor compatible with a CMOS manufacturing process wherein the power conversion efficiency of a photoelectric conversion part when the quantity of light is small is enhanced and the sensitivity can be enhanced.
A first solid-state image sensor according to the invention is based upon a solid-state image sensor provided with a photoelectric conversion part of a conductive type reverse to one conductive type of a semiconductor region, the reverse conductive type of a drain region formed in the semiconductor region and formed opposite to the photoelectric conversion part, MOSFET for control using the reverse conductive type of a region formed between the photoelectric conversion part and the drain region for a channel region for control and characterized in that the solid-state image sensor outputs the variation of the electric potential by electric charges generated in the photoelectric conversion part of the photoelectric conversion part via a source-follower amplifying circuit, and is characterized in that the first solid-state image sensor according to the invention has basic configuration that the photoelectric conversion part has a first photoelectric conversion part and a second photoelectric conversion part, the channel region for control is located between the second photoelectric conversion part and the drain region and MOSFET for setting constant potential using a region between the first photoelectric conversion part and the second photoelectric conversion part for a channel region for setting constant potential is formed between the first photoelectric conversion part and the second photoelectric conversion part. The solid-state image sensor according to the invention and having the basic configuration has the following various characteristics.
First, the first photoelectric conversion part is larger in area than the second photoelectric conversion part.
The potential of the channel region for setting constant potential is between the potential of the channel region for control when the voltage of a high level is applied to the channel region for control and the potential of the channel region for control when the voltage of a low level is applied.
At least one of the drain region, the first photoelectric conversion part and the second photoelectric conversion part is different from the others in the density of impurities and the depth of junction with the semiconductor region, the density of impurities in the drain region is higher than that of the first photoelectric conversion part and the second photoelectric conversion part, the depth of junction between the drain region and the semiconductor region is shallower than that between the first photoelectric conversion part or the second photoelectric conversion part and the semiconductor region and further, concretely, the first photoelectric conversion part and the second photoelectric conversion part are identical in the density of impurities and the depth of junction with the semiconductor region or are different in either of the density of impurities or the depth of junction with the semiconductor region.
The MOSFET for control is a depletion-type transistor in which current flows between the source and the drain even when voltage applied to the gate electrode is zero.
One conductive type of a cap semiconductor layer covers the surface of the first photoelectric conversion part.
The second photoelectric conversion part is connected to the gate of a source-follower transistor forming the source-follower amplifying circuit.
The parasitic capacity of the photoelectric conversion part when a minute signal is input can be reduced by providing the first and second photoelectric conversion parts as described above. Also, a second solid-state image sensor according to the invention is based upon a solid-state image sensor provided with a photoelectric conversion part for converting received light to a signal charge and is characterized in that the photoelectric conversion part is provided with one conductive type of a first semiconductor layer having first, second and third regions, a second conductive type of a second semiconductor layer which is formed in the first region in the first semiconductor layer and to which wiring for taking a signal charge is connected and the second conductive type of a third semiconductor layer formed in the third region in the first semiconductor layer with the second region between opposite to the second semiconductor layer.
Also, a third solid-state image sensor according to the invention is based upon a solid-state image sensor provided with a photoelectric conversion part for converting received light to a signal charge and is characterized in that the photoelectric conversion part is provided with one conductive type of a first semiconductor layer, a second conductive type of a second semiconductor layer which is formed in the first semiconductor layer and to which wiring for taking a signal charge is connected and the second conductive type of a third semiconductor layer formed in the first semiconductor layer apart from the second semiconductor layer.
The parasitic capacity of the photoelectric conversion part viewed from wiring when a minute signal is input can be reduced by forming the semiconductor layer forming the photoelectric conversion part by the plural semiconductor layers as described above.